VITA 65.0 slot configuration file SLT3-SWH6F8U-14.4.15

Complies with VITA 46.11 chassis management specifications and contains an IPMI controller chip. It supports IEEE 1588 PTP (Exact Time Protocol)

Up to 14 ETH. Ports and up to 12 PCIe ports, 1000base-KX/10Gbase-KR, 10Gbase-T (rear), 10Gbase-T/1 * QSFP+ (front)

3U VPX, expansion/data plane on P1 connectors, 4 * PCIe ports Gen1/2/3/4 (x4) - Each can be split into 2* x2 ports or combined (2* x8)

Expansion/data plane on P2 connectors, 2* PCIe ports Gen1/2/3/4 (x4) - Each port can be split into 2* x2 ports, or combined (1* x8)

Control plane for P2 connectors, 8 * 1000base-KX/10Gbase-KR, 1 * 10Gbase-T

Front panel control plane, QSFP + 1 * (4 * 40 * 10 G / 1 G), 1 * 10 m / 100 m/G / 2.5 G / 5 G / 10 gbase -t (RJ45), optional M2 module

The PCIe channels on the expansion/data plane are generated by high-performance non-blocking switches and provide non-transparent functions on each port

Supports partition, uplink, downlink, and non-transparent port modes

The Control Plane is based on the same technology as the ComEth4000e family, using Marvell's highly integrated system-on-chip (SoC) and programmable packet processor